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W972GG6JB
8.2
Clock Enable (CKE) Truth Table for Synchronous Transitions
CURRENT
STATE 2
Previous Cycle
(N-1)
CKE
1
Current Cycle
(N)
1
COMMAND (N) 3
RAS , CAS , WE , CS
ACTION (N) 3
NOTES
L
L
X
Maintain Power Down
11, 13, 15
Power Down
L
L
H
L
DESELECT or NOP
X
Power Down Exit
Maintain Power Down
4, 8, 11, 13
11, 15, 16
Self Refresh
L
H
DESELECT or NOP
Self Refresh Exit
4, 5, 9, 16
Bank(s) Active
All Banks Idle
H
H
H
L
L
L
DESELECT or NOP
DESELECT or NOP
REFRESH
Active Power Down
Entry
Precharge Power Down
Entry
Self Refresh Entry
4, 8, 10, 11,
13
4, 8, 10, 11,
13
6, 9, 11, 13
H
H
Refer to the Command Truth Table
7
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N – 1) was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the t XSNR period.
Read commands may be issued only after t XSRD (200 clocks) is satisfied.
6. Self Refresh mode can only be entered from the All Banks Idle state.
7. Must be a legal command as defined in the Command Truth Table.
8. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
9. Valid commands for Self Refresh Exit are NOP and DESELECT only.
10. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set
operations or Precharge operations are in progress. See section 7.9 "Power Down Mode" and section 7.3.7/7.3.8 "Self
Refresh Entry/Exit Command" for a detailed list of restrictions.
11. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the
valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of t IS + 2 x t CK + t IH .
12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
See section 7.2.4.
13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the
refresh requirements outlined in section 7.9.
14. CKE must be maintained HIGH while the SDRAM is in OCD calibration mode.
15. “X” means “don?t care (including floating around V REF )” in Self Refresh and Power Down. However ODT must be driven
high or low in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMR (1)).
16. V REF must be maintained during Self Refresh operation.
8.3
Data Mask (DM) Truth Table
FUNCTION
Write enable
Write inhibit
DM
L
H
DQS
Valid
X
NOTE
1
1
Note:
1. Used to mask write data, provided coincident with the corresponding data.
Publication Release Date: Nov. 29, 2011
- 32 -
Revision A02
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